Simulation and analysis of P/G noise in TSV based 3D MPSoC

3D multi-processor system-on-chip (3D MPSoC) can integrate more PUs together with shorter interconnection using vertical interconnection. It´s very important to analyze the power ground (P/G) noise induced by power gating in low power 2D MPSoC. Actually, 3D MPSoC will be more sensitive to P/G noise due to the vertical interconnection between different PUs. So the P/G noise induced by power gating needs more attention in low power 3D MPSoC design. In this paper, we firstly build a TSV-based 3D MPSoC P/G noise simulation platform. Then with the platform, several experiments are conducted to explore the P/G noise induced by power gating. At last, we investigate the proper distribution for P/G TSVs and the P/G noise propagation in 3D MPSoC.