Process optimization for a high gate trench MOS to minimize threshold voltage variation

Trench MOS devices are widely used in power applications. A novel high gate trench MOS design has the advantages of smaller gate resistance, faster switching, and lower power consumption. However, its low yield has hindered its mass production and application. In this work, we carried out in-depth analysis of the process flow in actual fab and found out the origin of the yield problem to be the electrostatic charge accumulation in the well region generated by friction during photoresist development step. The charges can affect the well doping concentration and in turn the threshold voltage of the MOS devices. Different approaches were proposed to solve the problem, among which rinse time reduction was found to be the most effective one at a low cost.. The process yield in HHNEC Fab2 in Shanghai was successfully raised up from below 60% to at least 98%. The research work would help facilitate the mass production and wide application of the novel high gate trench MOS.