Architecting connectivity for fine-grained 3-D vertically integrated circuits

Conventional CMOS technology is reaching fundamental scaling limits, and interconnection bottleneck is dominating IC power and performance. Migrating to 3-D integrated circuits, though promising, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Skybridge, a fine-grained 3-D IC fabric technology was recently proposed towards this aim, which offers a paradigm shift in technology scaling and design. In this paper we present specifically architected core Skybridge structures to enable fine-grained connectivity in 3-D intrinsically. We develop predictive models for interconnect length distribution for Skybridge, and use them to quantify the benefits in terms of expected reduction in interconnect lengths and repeater counts when compared to 2-D CMOS in 16nm node. Our estimation indicates up to 10x reduction in longest global interconnect length vs. 16nm 2-D CMOS, and up to 2 orders of magnitude reduction in the number of repeaters for a design consisting of 10 million logic gates. These results show great promise in alleviating interconnect bottleneck due to a higher degree of connectivity in 3-D, leading to shorter global interconnects and reduced power and area overhead due to repeater insertion.