Defect-oriented testing of analogue and mixed signal ICs

The high costs of testing analogue and mixed-signal Integrated Circuits (ICs) are driving a large research effort on test preparation in the IC design environment. In this paper, we highlight the usefulness of using a Defect-Oriented (DO) approach for test preparation, in order to generate and validate low-cost, high-quality tests. DO fault modeling is carried out using an Inductive Fault Analysis (IFA) strategy. Analogue fault simulation feasibility is analyzed. Analog Test Stimuli (ATS) generation for mixed-signal ICs is performed using digital BIST test hardware, available on-chip. A DO test environment and tools are presented. Simulation results are described, showing also how layout-driven Design-For-Testability (DFT) can enhance product quality and reliability, while cutting test costs