The control of polysilicon/silicon interface processed by rapid thermal anneal

The authors investigate the polysilicon-silicon interface of a bipolar transistor by correlating quantitative data from TEM (transmission electron microscope) atomic imaging with transistor electrical characteristics. Quantitative statistical analysis was performed over a wide area scan of TEM imaging to obtain information on interfacial oxide void radius, the density of those voids, and the local silicon epitaxial height at the emitter and extrinsic base polysilicon-silicon interfaces for various RTA (rapid thermal anneal) process conditions. Distributions of the emitter resistance and base resistance were measured to support the observed random process of interfacial oxide void formation. The effectiveness as a barrier to minority carrier transport as the oxide agglomerates with RTA processing was measured and correlated with fractions of void area at the interface. It was found that a 1-2% areal fraction of oxide void formation is necessary to obtain good control of low emitter resistance and to maintain a sufficient barrier for transistor reverse hole injection current