A clock-controlled self-stabilized voltage technique with high dynamic power reduction for portable multimedia applications

This paper proposes a clock-controlled self-stabilized voltage (CKVdd) technique to greatly reduce dynamic power consumption for portable multimedia applications. A normal CMOS circuit shows that dynamic power consumption increases proportionally to the clock frequency. CKVdd results in a lower-than-usual frequency dependency in dynamic power consumption. The proposed technique has been implemented in a multiple standard video decoder supporting JPEG, MPEG-1/2/4, and H.264 video decoding, which yields about 41% and 73% of power consumption as compared to the static CMOS implementation at 125MHz and 25MHz, respectively.