144-Gbit/s selector and 100-Gbit/s 4:1 multiplexer using InP HEMTs

Author

Suzuki, T. ; Nakasha, Y. ; Takahashi, T. ; Makiyama, K. ; Hirose, T. ; Takikawa, M.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

Volume

1

fYear

2004

fDate

6-11 June 2004

Firstpage

117

Abstract

144-Gbit/s operation of a selector circuit and 100-Gbit/s operation of a 4:1 multiplexer (MUX) using a 0.10μm InP HEMT technology were achieved. To increase the timing margin while reducing power consumption, two-phase lock architecture was used for the MUX. In addition, to align the timing between data and clock, a critical issue at a high bit-rate, a Gilbert-cell-type delay buffer was applied to the clock tree to precisely compensate for gate delay in data blocks. We also tested the maximum speed of the core of the MUX, the selector circuit, achieving 144-Gbit/s operation. As far as we know, this is the highest operational speed reported to date for a digital circuit.

Keywords

HEMT integrated circuits; clocks; digital circuits; integrated circuit design; logic circuits; 0.10 micron; 144 Gbits/s; 4:1 multiplexer; Gilbert-cell; HEMT technology; InP; clock tree; data blocks; delay buffer; digital circuit; gate delay; power consumption reduction; selector circuit; timing margin; two-phase lock architecture; Circuit testing; Clocks; Delay; Digital circuits; Energy consumption; HEMTs; Indium phosphide; MODFETs; Multiplexing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2004 IEEE MTT-S International

ISSN

0149-645X

Print_ISBN

0-7803-8331-1

Type

conf

DOI

10.1109/MWSYM.2004.1335816

Filename

1335816