Cache power and performance tradeoffs for embedded applications

As embedded applications have became more complex, design of embedded processors has created a research area for low power and yet high performance architectures. Power consumption is as important as performance in battery-powered embedded systems and in future, embedded processors are to process more computation-intensive applications with limited power budgets. Therefore, power consumption of theses processors will become more critical. According to the high contribution of memory access power in total power consumption of embedded systems, memory architecture of embedded systems strongly influences the system design objectives. Cache memories are usually used to improve the performance and power consumption by bridging the gap between the speed and power consumption of the main memory and CPU, therefore, the system performance and power consumption is severely related to the average memory access time and power consumption which makes the cache architecture as a major concern in designing embedded processors. Therefore, the embedded system designer requires a comprehensive design space exploration for memory architecture. In this paper we explore the design space of cache in embedded processors to find out the cache sizes which have the optimum performance/power consumption in embedded applications.