Zero-Value Caches: Cancelling Loads that Return Zero

The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating zero loads - loads accessing memory locations that contain the value ldquozerordquo - to improve performance and energy dissipation. Our study shows that such loads comprise as many as 18% of the total number of dynamic loads. We show that a significant fraction of zero loads ends up on the critical memory-access path in out-of-order cores. We propose a non-speculative microarchitectural technique - zero-value cache (ZVC) - to capitalize on zero loads and explore critical design options of such caches. We show that with modest investment, we can obtain speedups up to 78% and reduce the overall energy dissipation by up to 39%. Most importantly, zero-value caches never cause performance loss.