A high speed high jitter tolerant clock and data recovery circuit using crystal based dual PLL

The author describes a clock and data recovery circuit (CDRC) designed as the key function in an interface integrated circuit to support a fiber-optic local area network-the fiber distributed data interface (FDDI). A crystal-based dual PLL (phase-locked loop) locks to 125 Mb/s NRZI (nonreturn to zero inverted on ones) data and captures them. The jitter tolerance is 6.1 ns (8 ns bit period) to a random input data stream. The ECL-TTL and serial to parallel conversions are performed. This circuit operates at a single 5-V supply and dissipates 0.7 W. The CDRC was injected with a 6.1 ns peak-to-peak timing jitter at the random data input and still received FDDI data properly with BER(bit error rate) <2.5×10^-10