A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting

In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by applying the correlated level shifting (CLS) technique for the first four stages. Moreover, by obviating the need for a first stage S/H, power consumption was reduced considerably. The first stage of the pipeline has a 2.5-bit resolution, following six 1.5-bit stages with a 2-bit flash ADC at the end. For more power efficiency, stage scaling for the first three stages was also applied. Simulation results in HSPICE using a standard 0.18μm CMOS technology showed a SNDR and SFDR of 59.97dB and 64.8dB, respectively, for a 49.2MHz 2-Vp-p input signal. ADC power consumption excluding buffers and bonding-pads is 6.67mW from a 1.8V supply voltage.