A high performance multi-channel preamplifier ASIC

A novel preamplifier application-specific integrated circuit (ASIC) has been designed and built to improve performance of the Vertex Time Projection Chamber (VTPC) at the Fermilab Colliding Detector Facility (CDF). Design of the semicustom IC was completed using a Tektronix QuickChip 2S bipolar linear array. The ASIC has six channels on a chip and provides lower noise, higher gain, lower power, and lower mass packaging than the device which it replaces. Actual performance of the preamplifier was found to match very closely the simulated performance. To reduce the mass of the complete circuit board, bare IC dice were mounted directly on a G-10 substrate using chip on board techniques.<>