DocumentCode :
3458927
Title :
Rotating Register Allocation for Enhanced Pipeline Scheduling
Author :
Kim, Suhyun ; Moon, Soo-Mook
Author_Institution :
IBM T.J. Watson Res. Center, Seoul
fYear :
2007
fDate :
15-19 Sept. 2007
Firstpage :
60
Lastpage :
72
Abstract :
A rotating register file is a compiler-managed hardware renaming mechanism for overcoming the cross-iteration register overwrite problem in software pipelining [3J. It has primarily been used for software pipelining of straight-line and if-converted loops in the context of modulo scheduling. This paper proposes using rotating registers for software pipelining of loops with arbitrary control flows, in the context of enhanced pipeline scheduling (EPS). EPS can achieve a tight, variable initiation interval for such loops, but generates many hard-to-delete copies for handling the cross-iteration register overwrite problem. These copies may- cause a stall if they renamed multi-latency instructions, in addition to taking resources. In the prior work [9], these copies were removed by loop unrolling using an abstraction called extended live range (ELR). In this paper, we eliminate those copies by allocating rotating registers using the same ELR yet with a different interpretation, since both techniques share a similar intuition for copy elimination. There are some differences in building and using ELRs, though, which will also be discussed. We also discuss how existing rotating register allocation techniques cannot be easily adapted for EPS to handle loops with control flows. Our experimental results indicate that we can eliminate 50% of otherwise uncoalescible copies via rotating register allocation, which allows us to avoid a serious slowdown from latency handling and resource pressure without code expansion as in unrolling.
Keywords :
pipeline processing; program compilers; arbitrary control flows; compiler-managed hardware renaming mechanism; copy elimination; cross-iteration register overwrite problem; enhanced pipeline scheduling; extended live range; multilatency instructions; rotating register allocation; rotating register file; software pipelining; Delay; Hardware; Interference constraints; Moon; Parallel architectures; Pipeline processing; Resource management; VLIW;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architecture and Compilation Techniques, 2007. PACT 2007. 16th International Conference on
Conference_Location :
Brasov
ISSN :
1089-795X
Print_ISBN :
978-0-7695-2944-8
Type :
conf
DOI :
10.1109/PACT.2007.4336200
Filename :
4336200
Link To Document :
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