DocumentCode :
3459227
Title :
Early Register Release for Out-of-Order Processors with RegisterWindows
Author :
Quinones, Eduardo ; Parcerisa, Joan-Manuel ; Gonzalez, Antonio
Author_Institution :
Univ. Polytech. de Catalunya, Barcelona
fYear :
2007
fDate :
15-19 Sept. 2007
Firstpage :
225
Lastpage :
234
Abstract :
Register windows is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register requirements are normally increased for out-of-order execution because it requires registers for the in-flight instructions, in addition to the architectural ones. However, a large register file has an important cost in terms of area and power and may even affect the cycle time. In this paper we propose two early register release techniques that leverages register windows to drastically reduce the register requirements, and hence reduce the register file cost. Contrary to the common belief that out-of-order processors with register windows would need a large physical register file, this paper shows that the physical register file size may be reduced to the bare minimum by using this novel microarchitecture. Moreover, our proposal has much lower hardware complexity than previous approaches, and requires minimal changes to a conventional register window scheme. Performance studies show that the proposed technique can reduce the number of physical registers to the same number as logical registers plus one (minimum number to guarantee forward progress) and still achieve almost the same performance as an unbounded register file.
Keywords :
computer architecture; microprocessor chips; cycle time; early register release; hardware complexity; in-flight instructions; logical registers; memory operations; microarchitecture; out-of-order execution; out-of-order processors; physical register file; physical registers; procedure calls; register file cost; register requirements; register windows; Banking; Costs; Hardware; Microarchitecture; Out of order; Parallel architectures; Pipeline processing; Proposals; Registers; Runtime;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architecture and Compilation Techniques, 2007. PACT 2007. 16th International Conference on
Conference_Location :
Brasov
ISSN :
1089-795X
Print_ISBN :
978-0-7695-2944-8
Type :
conf
DOI :
10.1109/PACT.2007.4336214
Filename :
4336214
Link To Document :
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