DocumentCode
345947
Title
The index-permutation graph model for hierarchical interconnection networks
Author
Yeh, Chi-Hsiang ; Parhami, Behrooz
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear
1999
fDate
1999
Firstpage
48
Lastpage
55
Abstract
In this paper, we present the index-permutation (IP) graph model, and apply it to the systematic development of efficient hierarchical networks. We derive several classes of interconnection networks based on IP graphs to achieve desired properties; the results compare favorably with popular interconnection networks, as measured by topological (e.g., node degree and diameter) and algorithmic properties, and are particularly efficient in view of their sparse inter-module communication patterns. In particular, the diameters of suitably-constructed super-IP graphs, a subclass of IP graphs, are optimal within a factor of 1+o(1), given their node degrees. The IP graph model can also be used as a common platform that unifies the architectures and algorithms for a vast variety of interconnection networks
Keywords
multiprocessor interconnection networks; performance evaluation; algorithmic properties; hierarchical interconnection networks; hierarchical networks; index-permutation graph model; sparse inter-module communication patterns; systematic development; Algorithm design and analysis; Clustering algorithms; Genetic mutations; Hypercubes; Microwave integrated circuits; Multiprocessor interconnection networks; Network-on-a-chip; Parallel architectures; Parallel processing; Particle measurements;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing, 1999. Proceedings. 1999 International Conference on
Conference_Location
Aizu-Wakamatsu City
ISSN
0190-3918
Print_ISBN
0-7695-0350-0
Type
conf
DOI
10.1109/ICPP.1999.797387
Filename
797387
Link To Document