Analysis of the trade-off between input current quality and efficiency of high switching frequency PWM rectifiers

Due to their basic physical properties, power MOSFETs exhibit an output capacitance C_oss that is dependent on the drain-source voltage. This (nonlinear) parasitic capacitance has to be charged at turn-off of the MOSFET by the drain-source current in rectifier applications which yields input current distortions. As a detailed analysis shows, the nonlinear behavior of this capacitance is even more pronounced for modern super junction MOSFET devices. Whereas C_oss increases with increasing chip area the on-state resistance of the MOSFET decreases accordingly. Hence, a trade-off between efficiency and input current distortions exists. A detailed analysis of this effect considering different semiconductor technologies is given in this work and a Pareto curve in the η-THD space is drawn which clearly highlights this relationship. It is further shown, that the distortions mentioned can be reduced considerably by application of a proper feed-forward control signal counteracting the nonlinear switching delay due to C_oss. The theoretical considerations are verified by experimental results taken from 10 kW laboratory prototypes with the switching frequencies of 250 kHz, and 1MHz.