Device degradation due to stud bumping above the MOSFET region and the effect of annealing on the degradation

Author

Shimoyama, Nobuhiro ; Machida, Katsuyuki ; Shimaya, Masakazu ; Akiya, Hideo ; Kyuragi, Hakaru

Author_Institution

NTT Syst. Electron. Lab., Kanagawa, Japan

fYear

1997

fDate

8-10 Apr 1997

Firstpage

118

Lastpage

123

Abstract

This paper presents the effect of stud bumping above the MOSFET region on device degradation. Stud bumping above the MOSFET region generates an interface trap at the Si/SiO₂ interface and results in the degradation of mutual conductance for the N-channel MOSFET. The interface traps induced by stud bumping are apparently eliminated by both N₂ and H₂ annealing. However, the hot-carrier tolerance of H₂ annealing is one order of magnitude stronger than that of N₂ annealing. This effect is explained by terminating dangling bonds with hydrogen atoms

Keywords

MOSFET; annealing; dangling bonds; hot carriers; interface states; semiconductor device packaging; semiconductor device reliability; H₂; N-channel MOSFET; N₂; Si-SiO₂; annealing; dangling bonds; device degradation; hot carriers; interface traps; mutual conductance; stud bumping; Aluminum; Annealing; Bonding forces; Degradation; Gold; Large scale integration; MOSFET circuits; Power MOSFET; Stress; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 1997. 35th Annual Proceedings., IEEE International

Conference_Location

Denver, CO

Print_ISBN

0-7803-3575-9

Type

conf

DOI

10.1109/RELPHY.1997.584247

Filename

584247