Yield focused defect reduction methodology

The complexity of yield management continues to increase as the industry progresses towards larger wafers and smaller feature sizes. This progression is faster than ever seen before and the yield ramping window is closing in with the competitive nature of the industry. This phenomenon drives the need to use in line or “short loop” cycles to learn Yield more quickly than the classical approach of the strip back and backtrack. Another noticeable trend in the industry is the increased capital investment for in line defect inspection tools and complex strategies to detect defects in line. These tools generate an enormous amount of data that is difficult to convert into useful information for the Yield Engineer. Some fundamental questions asked of the Yield engineer are: What are the current Yield limiters of the Fab? What in line defects do we need to focus on? What is the Yield impact of each Scan level? What is the defect process capability of the line today? What in line defect levels do we need to drive our process to in order to meet Yield objectives? This paper describes a macro level in line to sort correlation methodology is currently used at AMD to systematically drive the defect related yield loss to the minimum level capable by the fab equipment and resources. The simplest way to describe the methodology is by using “long loop” feedback and verification activity to implement “short loop” cycles for quicker learning. The inspection strategy uses “product level” wafer scans at several inspection points in line and the wafer final test or sort data at the end of the line