A Novel Architecture to Identify the Microprocessor Chips by Implanting Timing-Fault Execution Unit

To protect the Intellectual Property of Integrated Circuit, We present a novel architecture which exploits and analyze error information produced by an embedded timing-fault execution unit in the data path of a microprocessor. As the timing of the fault execution circuit doesn´t meet microprocessor global timing requirement intentionally, the computation result appears randomly error and will depend on manufacturing process environment ultimately. Because of the variations of the manufacturing process, the error information will vary between different chips and will not be easily predicted. The timing-fault execution unit is a kind of PUF (Physical Unclonable Function) essentially, it utilizes setup time violations of D-type Flip-flop to identify and encrypt microprocessor. We verify the idea in Diligent Genesys Xilinx FPGA board by implanting one 32-bit timing-fault adder in a processor RTL model. It demonstrated that the error information produced by the timing fault unit is unique and has better random distribution, also the method can be easily integrated into the microprocessor design flow and Complex Challenge-Response pairs can be generated and captured by online high-level instruction streams. We argue the proposed architecture is a more practical and hopeful way to identify processor chips.