DocumentCode :
3460985
Title :
Simple design formula for parallel plate mode suppression by ground via-holes
Author :
Yuasa, Takeshi ; Nishino, Tamotsu ; Oh-hashi, Hideyuki
Author_Institution :
Mitsubishi Electr. Corp., Kanagawa, Japan
Volume :
2
fYear :
2004
fDate :
6-11 June 2004
Firstpage :
641
Abstract :
In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposing formula. It is shown that the technique is indispensable for designing optimal disposition of via-holes to minimize the area of the ground via-holes for desired performance.
Keywords :
finite element analysis; integrated circuit packaging; mode matching; radiofrequency integrated circuits; FEM simulation; finite element method; mode matching technique; multilayered RF circuit; optimal disposition; parallel plate mode suppression; quantitative evaluation; short-circuit; Circuit optimization; Computational modeling; Coupling circuits; Degradation; Dielectric substrates; Equivalent circuits; Millimeter wave circuits; Millimeter wave technology; Packaging; Radio frequency;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microwave Symposium Digest, 2004 IEEE MTT-S International
ISSN :
0149-645X
Print_ISBN :
0-7803-8331-1
Type :
conf
DOI :
10.1109/MWSYM.2004.1336067
Filename :
1336067
Link To Document :
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