• DocumentCode
    3461153
  • Title

    Formal verification as a technology transfer problem

  • Author

    Kurshan, R.

  • Author_Institution
    Cadence Design Syst., USA
  • fYear
    2004
  • fDate
    23-25 June 2004
  • Firstpage
    147
  • Lastpage
    150
  • Abstract
    Around 1990, various groups began to sense that the methods were sufficiently mature to warrant turning them into commercial tools. With ever-increasing design complexity, the cost of design testing was consuming an ever-greater portion of the design budget - as much as 80% - so more powerful methods for testing became badly needed. However, it soon became evident that what was useful in the hands of experts could not be directly converted into a useful commercial tool. The required methodology change included advancing verification to earlier stages of the development flow. This offered a big potential advantage for reducing development costs, since finding bugs earlier could save more costly fixes later. However, it required that developers participate in the verification process.
  • Keywords
    formal verification; software cost estimation; technology transfer; design budget; design complexity; design testing cost; development cost reduction; development flow; formal verification; technology transfer problem; Application software; Computer bugs; Electronic design automation and methodology; Formal verification; Hardware; Power system modeling; Project management; Protocols; Technology transfer; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Proceedings. Second ACM and IEEE International Conference on
  • Conference_Location
    San Diego, CA, USA
  • Print_ISBN
    0-7803-8509-8
  • Type

    conf

  • DOI
    10.1109/MEMCOD.2004.1459839
  • Filename
    1459839