DocumentCode
3461423
Title
Design challenges in nanometric embedded memories
Author
Rennie, David J. ; Shakir, Tahseen ; Sachdev, Manoj
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
fYear
2009
fDate
6-8 Nov. 2009
Firstpage
1
Lastpage
8
Abstract
Embedded memories comprise over half the die area in modern SOC ICs. These circuits enable large gains in performance, however they bring with them many challenges. As CMOS technology scales deep into the nano-metric region the size and density of embedded memories are increasing, both of which result in increased challenges for designers. This paper describes the design challenges intrinsic to the implementation of embedded memories in modern nanometric CMOS processes.
Keywords
CMOS memory circuits; integrated circuit design; integrated memory circuits; system-on-chip; CMOS technology; SOC integrated circuit; die area; integrated circuit design; nanometric CMOS process; nanometric embedded memories; CMOS integrated circuits; CMOS memory circuits; CMOS process; CMOS technology; Circuits and systems; Delay; Joining processes; MOSFETs; Random access memory; Signal design; CMOS; SRAM; scaling; soft error; variability;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Circuits and Systems (SCS), 2009 3rd International Conference on
Conference_Location
Medenine
Print_ISBN
978-1-4244-4397-0
Electronic_ISBN
978-1-4244-4398-7
Type
conf
DOI
10.1109/ICSCS.2009.5412617
Filename
5412617
Link To Document