DocumentCode
3462153
Title
A Flexible Digital Receiver Architecture For Radar Applications
Author
Deitersen, Holger
Author_Institution
EADS Germany GmbH, Defence Electronics, Naval & Ground Radar Signal Processing, Woerthstrasse 85, 89077 Ulm. email: holger.deitersen@eads.com
fYear
2006
fDate
24-26 May 2006
Firstpage
1
Lastpage
4
Abstract
This paper presents a modular architecture of a digital receiver for radar applications. The focal point will be the concept of the digital part including the A to D conversion (ADC) process and the effective embedding and integration into the Radar Processor environment. All used components should be "commercial-off-the shelf" (COTS) like ADC-mezzanine boards and processor boards in order to minimize development costs.
Keywords
Bandwidth; Clocks; Clutter; Degradation; Digital signal processing; Frequency; Object detection; Radar applications; Sampling methods; Signal sampling;
fLanguage
English
Publisher
ieee
Conference_Titel
Radar Symposium, 2006. IRS 2006. International
Conference_Location
Krakow, Poland
Print_ISBN
978-83-7207-621-2
Type
conf
DOI
10.1109/IRS.2006.4338019
Filename
4338019
Link To Document