Retractile clock-powered logic

Author

Tzartzanis, Nestoras ; Athas, William

Author_Institution

Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA

fYear

1999

fDate

17-17 Aug. 1999

Firstpage

18

Lastpage

23

Abstract

Retractile clock-powered logic is presented as a low-overhead energy-recovery logic style. It uses energy-efficient clock-steering circuits, pass-transistor logic, and a four-phase clocking scheme to recover energy from all circuit nodes but the latches. A 16-bit retractile clock-powered adder is described and evaluated through HSPICE simulations. The simulation results indicate that this approach can offer superior energy vs. delay performance but the benefit depends strongly on the switching activity of the clock-powered nodes.

Keywords

CMOS logic circuits; adders; logic design; low-power electronics; timing; HSPICE simulations; clock-powered nodes; energy-efficient clock-steering circuits; four-phase clocking scheme; low-overhead energy-recovery logic style; pass-transistor logic; retractile clock-powered adder; retractile clock-powered logic; switching activity; Adders; CMOS logic circuits; Clocks; Driver circuits; Energy efficiency; Latches; Logic circuits; Logic design; Permission; Uniform resource locators;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on

Conference_Location

San Diego, CA, USA

Print_ISBN

1-58113-133-X

Type

conf

Filename

799403