• DocumentCode
    3462626
  • Title

    TILE64 - Processor: A 64-Core SoC with Mesh Interconnect

  • Author

    Bell, Shane ; Edwards, Bruce ; Amann, John ; Conlin, Rich ; Joyce, Kevin ; Leung, Vince ; MacKay, John ; Reif, Mike ; Bao, Liewei ; Brown, John ; Mattina, Matthew ; Miao, Chyi-Chang ; Ramey, Carl ; Wentzlaff, David ; Anderson, Walker ; Berger, Ethan ; Fai

  • Author_Institution
    Tilera, Westborough, MA
  • fYear
    2008
  • fDate
    3-7 Feb. 2008
  • Firstpage
    88
  • Lastpage
    598
  • Abstract
    The TILE64TM processor is a multicore SoC targeting the high-performance demands of a wide range of embedded applications across networking and digital multimedia applications. A figure shows a block diagram with 64 tile processors arranged in an 8x8 array. These tiles connect through a scalable 2D mesh network with high-speed I/Os on the periphery. Each general-purpose processor is identical and capable of running SMP Linux.
  • Keywords
    general purpose computers; microprocessor chips; system-on-chip; 2D mesh network; SMP Linux; general-purpose processor; mesh interconnect; system-on-chip; Bandwidth; Communication system control; Engines; Microprocessors; Read-write memory; Registers; Silicon; Tail; Telecommunication traffic; Tiles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-1-4244-2010-0
  • Electronic_ISBN
    978-1-4244-2011-7
  • Type

    conf

  • DOI
    10.1109/ISSCC.2008.4523070
  • Filename
    4523070
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3462626