The impact of stress enhanced technology for sub-90nm SOI MOSFETs

Author

Yeh, Wen-Kuan ; Lai, Chieh-Ming ; Lin, Chien-Ting ; Fang, Yean-Kuen

Author_Institution

Dept. of Electr. Eng., Kaohsiung Nat. Univ.

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

112

Lastpage

115

Abstract

For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length of diffusion (LOD) to control the tensile and compressive stress in channel regions were developed. In this work, in order to investigate the interactive stress effects of GC layer film thickness, LOD and gate width on device´s characteristic and hot-carrier reliability; devices with various GC layer (1100A, 700A, SiN380), LOD (0.45mum ~4.5mum) and width (0.18mum~10mum) were fabricated. It is found that devices with 700A GC layer layer (appropriate tensile stress), 4.5 mum LOD (low compressive stress) and 0.18mum gate width (narrow width) possess the better performance

Keywords

MOSFET; hot carriers; nanoelectronics; semiconductor technology; silicon-on-insulator; 0.18 nm; SOI MOSFET; hot-carrier reliability; length-of-diffusion; stress control; stress enhanced technology; tensile stress gate capping layer; CMOSFETs; Compressive stress; Degradation; Hot carrier effects; Hot carriers; MOSFET circuits; Silicon compounds; Substrates; Tensile stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306091

Filename

4098035