Effective suppression of fermi level pinning in poly-Si/HfO/sub 2/ gate stack by using poly-SiGe gate

Author

Yu, Xiongfei ; Yu, Mingbin ; Zhu, Chunxiang

Author_Institution

Dept. of Electr. & Comput. Eng., Singapore Nat. Univ.

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

149

Lastpage

151

Abstract

In this work, it was demonstrated that the Fermi level pinning in poly-Si/HfO₂ can be effectively suppressed by using poly-SiGe gate. Threshold voltage of -1.02 V in poly-Si/HfO₂ PFET was tuned to -0.81 V in poly-Si/Al₂O₃/HfO₂, and further reduced to -0.49 V in poly-Si/poly-SiGe/Al₂O₃/HfO₂. At the same time, V_th of 0.3 V for NFET was achieved in this poly-SiGe gate stack. Moreover, V_th stability was remarkably improved by using poly-SiGe gate and Al₂O₃ capping layer. The improvements shown in this poly-SiGe gate stack could be due to the suppressed formation of oxygen vacancies

Keywords

Fermi level; Ge-Si alloys; aluminium compounds; field effect transistors; hafnium compounds; silicon; -0.49 V; -0.81 V; -1.02 V; 0.3 V; Fermi level pinning suppression; PFET; Si-Al₂O₃-HfO₂; Si-SiGe-Al₂O₃-HfO₂; gate stack; threshold voltage stability; Aluminum oxide; Annealing; Buffer layers; Dielectrics; Germanium silicon alloys; Hafnium oxide; Microelectronics; Silicon germanium; Stability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306123

Filename

4098045