DocumentCode :
346310
Title :
Way-predicting set-associative cache for high performance and low energy consumption
Author :
Inoue, Koji ; Ishihara, Tohru ; Murakami, Kazuaki
Author_Institution :
Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
fYear :
1999
fDate :
17-17 Aug. 1999
Firstpage :
273
Lastpage :
275
Abstract :
This paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches. By accessing only a single cache way predicted, instead of accessing all the ways in a set, the energy consumption can be reduced. This paper shows that the way-predicting set-associative cache improves the ED (energy-delay) product by 60-70% compared to a conventional set-associative cache,.
Keywords :
cache storage; delays; integrated circuit design; microprocessor chips; energy consumption; energy-delay product; on-chip cache; set-associative cache; way prediction; Computer science; Degradation; Delay effects; Energy consumption; Filters; Hardware; Permission; Power engineering and energy; Proposals; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on
Conference_Location :
San Diego, CA, USA
Print_ISBN :
1-58113-133-X
Type :
conf
Filename :
799456
Link To Document :
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