Novel SJ-LDMOS with partial N-buried layer for SPIC applications

Author

Chen, Wanjun ; Zhang, Bo ; Li, Zhaoji

Author_Institution

Center of IC Design, China Univ. of Electron. Sci. & Technol., Chengdu

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

251

Lastpage

253

Abstract

A novel super-junction (SJ) LDMOS (SJ-LDMOS) with partial N-buried layer is proposed which allows high breakdown voltage (BV) and low on-resistance (Ron). The proposed structure overcomes the substrate-assisted-depletion effect thus achieving the charge compensation between the n and p pillars as well as a uniform electric field distribution in the drift region in the off-state. The N-buried layer also provides a low current path in the on-state. In addition, the proposed device is compatible with smart power technology

Keywords

MOSFET circuits; buried layers; power integrated circuits; SJ-LDMOS; SPIC applications; charge compensation; partial N-buried layer; smart power integrated circuits; smart power technology; substrate-assisted-depletion effect; super-junction LDMOS; uniform electric field distribution; Application specific integrated circuits; Degradation; Doping; Electronic ballasts; Motor drives; Neodymium; Power integrated circuits; Switched-mode power supply; Tellurium;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306176

Filename

4098076