Digital design with minimal number of scan flip-flops

In this paper we present an efficient algorithm for the selection of flip-flops for partial scan design. The emphasis of the research is not on finding the (Minimum Feedback Vertex Set) MFVS set that makes the circuit acyclic, but rather a minimal set of vertices that opens long feedback loops while keeping the fault coverage within user-defined acceptable limit. The algorithm determines the vertex set to open loops of length K or higher. We applied the algorithm to several ISCAS-89 benchmark circuits. For K=1 and except for one circuit, the number of flip-flops to be scanned is the same or slightly higher than the previously published results. However as K increases, our results indicated that it is not necessary to determine the MFVS, since a reduction of the hardware overhead by about 50% corresponds to a fault coverage reduction of only 2% from its value for K=1