Semi-custom VLSI design for RNS multipliers using combinational logic approach

Design of Residue Number system Multipliers has received considerable attention in the last few years. This paper presents a new approach for designing modular multipliers using combinational logic technique. The idea is based on constructing a truth table whose inputs are the bits of the multiplicand and the multiplier. The outputs are the bits of the modular product realizing any minimized boolean function is achieved using two levels of gates. A VLSI implementation of module 5 has been accomplished. Compared to most recent developed approach, our new technique requires less integrated circuit area and operates at a higher speed