Design and VLSI implementation of CSD filter for pre-processing of image signals

Author

Yang, Yoon Gi ; Cho, Nam Ik ; Lee, Sang Uk

Author_Institution

Samsung Electron. Co. Ltd., Seoul, South Korea

Volume

2

fYear

1996

fDate

13-16 Oct 1996

Firstpage

960

Abstract

In this paper, we investigate the design and VLSI implementation of CSD (canonic signed digit) coefficient filters for high speed digital filtering. First, CSD coefficient filters are designed, which can be used as format conversion filters in place of the ones employed for the MPEG2 TM5 (test model 5). It is shown that the proposed CSD filters perform better than the conventional one, while having lower hardware complexity. Second, the pipelined bit-serial and bit-parallel architectures for the CSD filter are proposed and verified through the VHDL simulation

Keywords

VLSI; digital filters; image processing; CSD filter; VHDL simulation; VLSI design; canonic signed digit coefficient filter; format conversion; hardware complexity; high speed digital filter; image signal pre-processing; pipelined bit-parallel architecture; pipelined bit-serial architecture; Degradation; Design methodology; Digital filters; Frequency; HDTV; Hardware; Image converters; Signal design; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on

Conference_Location

Rodos

Print_ISBN

0-7803-3650-X

Type

conf

DOI

10.1109/ICECS.1996.584545

Filename

584545