Title :
Automatic synthesis of an 8-bit CPU with 100% on-line error detection capability
Author :
Markas, T. ; Edwards, E. ; Wang, S. ; Medero, J. ; Kanopoulos, N.
Author_Institution :
Data Commun. Technol., Research Triangle Park, NC, USA
Abstract :
This paper presents the use of a CAD system that allows the automatic synthesis of integrated circuits with on-line, 100% error detection capability. An 8-bit CPU serves as a benchmark to demonstrate the circuit technology used to automatically synthesize this type of circuit. The paper presents results on the actual design of the benchmark circuit and the use of the CAD system that made the design possible
Keywords :
CMOS digital integrated circuits; circuit CAD; error detection; integrated circuit design; logic CAD; microprocessor chips; 8 bit; CAD system; CPU design; DCVS gate synthesis tool; IC design; automatic synthesis; dual-rail circuit design; integrated circuits; online error detection capability; Boolean functions; Circuit faults; Circuit synthesis; Cost function; Design automation; Design methodology; Libraries; Logic functions; Semiconductor device modeling; Tree graphs;
Conference_Titel :
Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on
Conference_Location :
Rodos
Print_ISBN :
0-7803-3650-X
DOI :
10.1109/ICECS.1996.584547
