A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC

The CDR circuit is fabricated in 0.25 mum SiGe BiCMOS technology. The low-speed digital blocks, such as the frequency detector, the up/down counter, the modulator, and the dither generator, are developed using CMOS transistors. The LPF used in the DAC is integrated in the chip. Two power supplies, 3.3 V for bipolar transistors and 1.8 V for CMOS, are used. PONs such as 10G-EPON systems require a burst-mode CDR circuit for upstream transmission that has an instantaneous response, tolerance to long consecutive-identical digits (CIDs), and high jitter tolerance. In this paper, a burst-mode CDR circuit achieves instantaneous locking of 1b, CID tolerance of 160b, and jitter tolerance of 0.27UIpp at 10.3125Gb/s operation. These characteristics are provided by a CDR architecture using a single gated VCO (GVCO) and DeltaSigma DAC.The simple architecture of the GVCO-based bust-mode CDR circuit provides instantaneous phase locking, which reduces the overhead time and increases the transmission efficiency.