Impact of chip-package interaction on reliability of Cu/ultra low-k interconnects for 65nm technology and beyond

The die attach process to flip chip package using Pb-free solder can impact the mechanical reliability of Cu/ultra low-k interconnects for 65nm technology and beyond. In this study, chip-package interaction (CPI) during solder reflow before underfilling was investigated by using a 3D multilevel submodeling method and by calculating the crack driving force at the specific interface in the Cu/Ultra low-k interconnects. We compared first the CPI for a CVD-OSG (k = 3.0) with MSQ (k = 2.7) and spin-on polymer (k = 2.7) to investigate how the material properties affects the interconnect reliability. Then the study was extended to porous MSQ (k = 2.3) to examine CPI for the 65 nm node and beyond. Packaging effects were significantly changed with different Young´s modulus but was not changed with different coefficient of thermal expansion (CTE). Further results are shown with different interconnect structures. Finally, requirements of the mechanical properties of low-k interlayer dielectric (ILD) and the interconnect structure for improving interconnect reliability are discussed