A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC

Author

Van Elzakker, Michiel ; Van Tuijl, Ed ; Geraedts, Paul ; Schinkel, Daniel ; Klumperink, Eric ; Nauta, Bram

Author_Institution

Univ. of Twente, Enschede

fYear

2008

fDate

3-7 Feb. 2008

Firstpage

244

Lastpage

610

Abstract

An ADC for energy scavenging is proposed using a charge-redistribution DAC, a dynamic 2-stage comparator, and a delay-line-based controller realized in CMOS. The charge-redistribution DAC can be used in a simple way to make a SAR ADC. The 10b differential ADC uses bootstrapped NMOS devices to sample the differential input voltage onto two identical charge-redistribution DACs. The test chip is fabricated in a 65nm CMOS process. In this ADC, the MSB is set in between the sampling phase and the first comparison, saving energy and time.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); delay lines; digital-analogue conversion; CMOS process; charge-redistribution ADC; charge-redistribution DAC; chip fabrication; delay-line-based controller; differential ADC; dynamic two-stage comparator; energy scavenging; power 1.9 muW; size 65 nm; Capacitors; Clocks; Delay; Inverters; MOS devices; Sampling methods; Signal generators; Switches; Tin; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-2010-0

Electronic_ISBN

978-1-4244-2011-7

Type

conf

DOI

10.1109/ISSCC.2008.4523148

Filename

4523148