Defect passivation and interface engineering for high-K gate dielectric device performance and reliability enhancement

Using a fluorinated high-k/metal gate stack combined with a stress relieved pre-oxide (SRPO) pretreatment before high-k deposition, the authors show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern. The novel fluorinated gate stack device exceeds the PBTI and NBTI targets with sufficient margin and has electron mobility comparable to the best polySi/SiON device on bulk Si reported so far