DocumentCode
3464066
Title
Design techniques and performance of an LSI-based 2B1Q transceiver
Author
Arai, M. ; Yamaguchi, M. ; Nakagawa, F. ; Shibata, H. ; Kanemasa, A. ; Makabe, T. ; Koike, S.
Author_Institution
NEC Corp., Chiba, Japan
fYear
1988
fDate
28 Nov-1 Dec 1988
Firstpage
778
Abstract
Examines a 2B1Q transceiver system which was selected as the standard for an ISDN (integrated services digital network) loop transmission systems in the US. An LSI-based 2B1Q transceiver consisting of three LSI chips has been developed. Echo tail suppression, receiver design to configure stable decision feedback equalizer (DFE) operation and to improve NEXT performance, and the accurate analog front end circuit are discussed. Experimental results show that satisfactory performance is obtained
Keywords
ISDN; codes; equalisers; feedback; large scale integration; transceivers; ISDN; LSI-based 2B1Q transceiver; NEXT performance; analog front end circuit; echo tail suppression; integrated services digital network; loop transmission systems; receiver design; stable decision feedback equalizer; Circuits; Decision feedback equalizers; Echo cancellers; Finite impulse response filter; IIR filters; ISDN; Large scale integration; Tail; Timing; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Global Telecommunications Conference, 1988, and Exhibition. 'Communications for the Information Age.' Conference Record, GLOBECOM '88., IEEE
Conference_Location
Hollywood, FL
Type
conf
DOI
10.1109/GLOCOM.1988.25944
Filename
25944
Link To Document