• DocumentCode
    3464107
  • Title

    A 170GB/s 16Mb Embedded DRAM with Data-Bus Charge-Recycling

  • Author

    Hardee, Kim ; Parris, Michael ; Jones, O. Fred ; Butler, Doug ; Mound, Mike ; Jones, G.W. ; Egging, Tim ; Arakawa, Tomofumi ; Sasahara, Katsuhiko ; Taniguchi, Kazuo ; Miyabayashi, Masayuki

  • Author_Institution
    United Memories, Colorado Springs, CO
  • fYear
    2008
  • fDate
    3-7 Feb. 2008
  • Firstpage
    272
  • Lastpage
    612
  • Abstract
    Embedded DRAM is well suited for integrated graphics applications that require extremely high bandwidth and large amounts of memory. High per-pin data rate, very wide I/O, and concurrent read/write together provide a high total data rate. The highest previous total data rate for a 16Mb macro reported at this conference is 92GB/s. This work demonstrates a 16Mb DRAM macro test chip with data rates of 2.66Gb/s/pin and 170GB/s total.
  • Keywords
    DRAM chips; system buses; DRAM macro test chip; byte rate 170 GByte/s; concurrent read/write; data-bus charge-recycling; embedded DRAM; integrated graphics; memory size 16 MByte; per-pin data rate; very wide I/; Circuits; Clocks; Energy consumption; Error correction codes; Frequency; Graphics; Random access memory; Recycling; Timing; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-1-4244-2010-0
  • Electronic_ISBN
    978-1-4244-2011-7
  • Type

    conf

  • DOI
    10.1109/ISSCC.2008.4523162
  • Filename
    4523162
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3464107