A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Author

Bae, Seung-Jun ; Sohn, Young-Soo ; Park, Kwang-Il ; Kim, Kyoung-Ho ; Chung, Dae-Hyun ; Kim, Jin-Gook ; Kim, Si-Hong ; Park, Min-Sang ; Lee, Jae-Hyung ; Bang, Sam-Young ; Lee, Ho-Kyung ; Park, In-Soo ; Kim, Jae-Sung ; Kim, Dae-Hyun ; Kim, Hye-Ran ; Shin, Y

Author_Institution

Samsung Electron., Hwasung

fYear

2008

fDate

3-7 Feb. 2008

Firstpage

278

Lastpage

613

Abstract

Demand for high-speed DRAM in graphics application pushes a single-ended I/O signaling to operate up to 6Gb/s. To maintain the speed increase, the GDDR5 specification shifts from GDDR3/4 with respect to forwarded clocking, data training for write and read de-skewing, clock training, channel-error detection, bank group and data coding. This work tackles challenges in GDDR5 such as clock jitter and signal integrity.

Keywords

DRAM chips; clocks; intersymbol interference; jitter; GDDR5 graphics DRAM; bank group; channel-error detection; clock jitter; clock training; command clock; data coding; data training; intersymbol interference; signal integrity; Bandwidth; Clocks; Feedback; Filters; Graphics; Intersymbol interference; Phase locked loops; Random access memory; Resistors; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-2010-0

Electronic_ISBN

978-1-4244-2011-7

Type

conf

DOI

10.1109/ISSCC.2008.4523165

Filename

4523165