• DocumentCode
    3464301
  • Title

    Software acceleration using coprocessors: is it worth the effort?

  • Author

    Edwards, Martyn

  • Author_Institution
    Comput. Dept., Univ. of Manchester Inst. of Sci. & Technol., UK
  • fYear
    1997
  • fDate
    24-26 Mar 1997
  • Firstpage
    135
  • Lastpage
    139
  • Abstract
    A commonly accepted technique in hardware/software co-design is to implement as many system functions as possible in software and to move performance-critical functions into special-purpose external hardware in order to either satisfy timing constraints or reduce the overall execution time of a program-this is known as “software acceleration”. This paper investigates the limits to the performance enhancements obtainable using software acceleration techniques. A practical target architecture, based on the use of programmable logic, is used to illustrate the problems associated with software acceleration. It is shown that, normally, little benefit can be obtained by applying software acceleration methods to general-purpose applications. Whereas software acceleration can profitably be used in a limited number of special-purpose applications, a designer would probably be better off developing ASIP (application-specific instruction-set processor) components, based on heterogeneous multiprocessor architectures
  • Keywords
    PLD programming; application specific integrated circuits; computer architecture; coprocessors; high level synthesis; software engineering; software performance evaluation; timing; ASIP components; application-specific instruction-set processor; computer architecture; coprocessors; hardware/software codesign; heterogeneous multiprocessor architectures; performance enhancements; performance-critical functions; program execution time reduction; programmable logic; software acceleration; special-purpose applications; special-purpose external hardware; system functions; timing constraints; Acceleration; Application software; Application specific processors; Computer architecture; Coprocessors; Hardware; Programmable logic arrays; Programmable logic devices; Software performance; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware/Software Codesign, 1997. (CODES/CASHE '97), Proceedings of the Fifth International Workshop on
  • Conference_Location
    Braunschweig
  • ISSN
    1092-6100
  • Print_ISBN
    0-8186-7895-X
  • Type

    conf

  • DOI
    10.1109/HSC.1997.584592
  • Filename
    584592