Laser annealing technology and device integration challenges

We investigated impacts of halo and deep source/drain junction on the performance of devices that were fabricated by non-melt laser spike annealing (LSA). By optimizing both profiles, we achieved 10%-better performance compared to those by the conventional LSA that have only the optimized gate-S/D overlap structure. The hot carrier degradation was also reduced to an RTA-comparable level by the halo optimization. We have also developed a novel laser thermal processing (LTP) that dramatically enhances laser exposure window by controlling the heating process in a self-limiting way (SL-LTP). Its effectiveness was also verified in 50-nm gate CMOS devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit