Author :
Lin, Yu-Kun ; Li, De-Wei ; Lin, Chia-Chun ; Kuo, Tzu-Yun ; Wu, Sian-Jin ; Tai, Wei-Cheng ; Chang, Wei-Cheng ; Chang, Tian-Sheuan
Abstract :
High-profile H.264 has been adopted as the major coding standard in popular high definition video due to its excellent coding efficiency. Several implementations have been developed ((Y. W. Huang, et al., 2005), (H.C. Chang, et al., 2007), (T.C. Chen, et al., 2007)), but, their performance is limited to baseline 720p (Y. W. Huang, et al., 2005),(H.C. Chang, et al., 2007) or SDTV (T.C. Chen, et al., 2007). The main stream 1080p high-profile application presents a series of new design challenges in throughput, cost and power because of at least a 4x higher complexity than in the 720p baseline. Thus, a 0.13mum 1080p high-profile H.264 video encoder is presented with 10mm2 core and 242 mW power. Compared to a state-of-the-art 720p baseline design (H.C. Chang, et al., 2007), this design achieves a 46.7% and 54% reduction in area and power, respectively. These savings are from parallelism enhanced throughput and a cross-stage sharing pipeline.
Keywords :
digital signal processing chips; discrete cosine transforms; motion estimation; video coding; H.264/AVC high-profile encoder chip; discrete cosine transform; fractional motion estimation; integer motion estimation; nonsampling reference memory sharing; power 242 mW; video encoder; Automatic voltage control; Circuits; Costs; Energy consumption; Frequency; HDTV; Hardware; Motion estimation; Testing; Throughput;
