• DocumentCode
    3464524
  • Title

    CMOS shallow trench isolation x-stress effect on channel width for 130nm technology

  • Author

    Tan, Philip Beow Yew ; Kordesch, Albert Victor ; Sidek, Othman

  • Author_Institution
    Silterra Malaysia Sdn. Bhd., Kulim
  • fYear
    2006
  • fDate
    Oct. 2006
  • Firstpage
    478
  • Lastpage
    480
  • Abstract
    In this paper, we investigated the compressive mechanical STI x-stress (in the direction of channel length) on channel width. When the channel width becomes narrower, the compressive STI y-stress effect become more severe and causes STI x-stress has lower effect on NMOS Idsat but has higher effect on PMOS Idsat. This means that the amount of NMOS Idsat decrement due to x-stress become less but the amount of PMOS Idsat increment due to x-stress become higher when y-stress increases (narrower channel width)
  • Keywords
    CMOS integrated circuits; isolation technology; nanotechnology; stress effects; 130 nm; CMOS shallow trench isolation; channel width; compressive STI y-stress effect; compressive mechanical STI x-stress effect; CMOS technology; Charge carrier processes; Compressive stress; Electron mobility; Isolation technology; MOSFETs; Semiconductor device modeling; Semiconductor process modeling; Silicon on insulator technology; Thermal stresses;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    1-4244-0160-7
  • Electronic_ISBN
    1-4244-0161-5
  • Type

    conf

  • DOI
    10.1109/ICSICT.2006.306306
  • Filename
    4098141