A vector quantization circuit for trainable neural networks

Vector quantization systems are usually implemented in hardware by realization of an algorithm, usually exploiting accelerated techniques for codebook search. These implementations are not well suited for the use as analog electronic neural networks building blocks. This paper presents an analog, fully parallel implementation of vector quantization exploiting a large number of simple processors. The circuit features large-dimensional (64) vectors and a medium-to-high density of units per chip. Moreover, the winner-take-all block features a linear output that replicates the value of the winning distance, in addition to the winner´s location flag. This makes it possible to use the system in trainable networks without need for further circuitry