• DocumentCode
    3464718
  • Title

    Steady-state time-domain analysis method with variable time step integration

  • Author

    Jokinen, Hannv ; Valtonen, Martti

  • Author_Institution
    Fac. of Electr. Eng., Helsinki Univ. of Technol., Espoo, Finland
  • Volume
    2
  • fYear
    1996
  • fDate
    13-16 Oct 1996
  • Firstpage
    1139
  • Abstract
    A method for steady-state time-domain analysis with variable time step integration is presented. The algorithm proposed is based on using the changes of the sources as initial data of the analysis and subsequently using the truncation error with optimization. An example is given to demonstrate that the novel method is efficient, and sufficiently fast to be used in circuit design. The simulation results show good agreement with those obtained by harmonic balance, steady-state time-domain with a fixed time step integration, and transient analysis
  • Keywords
    circuit analysis computing; integration; nonlinear network analysis; optimisation; time-domain analysis; optimization; steady-state time-domain analysis method; truncation error; variable time step integration; Algorithm design and analysis; Circuit theory; Data analysis; Finite wordlength effects; Laboratories; Nonlinear circuits; Nonlinear equations; Steady-state; Time domain analysis; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on
  • Conference_Location
    Rodos
  • Print_ISBN
    0-7803-3650-X
  • Type

    conf

  • DOI
    10.1109/ICECS.1996.584623
  • Filename
    584623