Title :
A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering
Author :
Yu, Xueyi ; Sun, Yuanfeng ; Zhang, Li ; Rhee, Woogeun ; Wang, ZhiHua
Author_Institution :
Tsinghua Univ., Beijing
Abstract :
This paper describes a noise filtering method for quantization noise reduction that is not sensitive to PVT variations. The resulting fractional-N PLL clock generator is the first one demonstrated with an oversampling ratio (OSR) of about 10.
Keywords :
FIR filters; UHF circuits; delta-sigma modulation; filtering theory; phase locked loops; pulse generators; quantisation (signal); signal denoising; signal sampling; FIR-embedded noise filtering method; fractional-N PLL clock generator; low-OSR delta-sigma modulation; quantization noise reduction; Bandwidth; Clocks; Filtering; Finite impulse response filter; Jitter; Noise generators; Noise shaping; Phase frequency detector; Phase locked loops; Phase noise;
Conference_Titel :
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-2010-0
Electronic_ISBN :
978-1-4244-2011-7
DOI :
10.1109/ISSCC.2008.4523199
