Power consumption optimization of 8 bit, 2 MHz voltage scaling subranging CMOS 0.5 μm DAC

Author

Maloberti, Franco ; Rivoir, Roberto ; Torelli, Guido

Author_Institution

Dipt. di Elettronica, Pavia Univ., Italy

Volume

2

fYear

1996

fDate

13-16 Oct 1996

Firstpage

1162

Abstract

We present the design of an 8-bit voltage-scaling, subranging digital-to-analog converter with a current-biased floating fine ladder. The basic structure has been analyzed and optimized for the best trade-off between conversion speed and power dissipation. This allowed us to design a 4+4 bit converter capable to drive 4 pF with 200 μA current consumption running at 2 MHz. Circuit simulations on a 0.5 μm, 3.3 V single-supply CMOS digital process show that the above performances are fully achieved even in worst-case process conditions

Keywords

CMOS integrated circuits; circuit optimisation; digital-analogue conversion; integrated circuit design; 0.5 micron; 2 MHz; 200 muA; 3.3 V; 4 pF; 8 bit; CMOS DAC; conversion speed; current-biased floating fine ladder; digital-to-analog converter; power consumption optimization; power dissipation; single-supply CMOS digital process; voltage scaling subranging DAC; CMOS digital integrated circuits; CMOS process; Digital-analog conversion; Electronics industry; Energy consumption; Industrial electronics; Power dissipation; Resistors; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on

Conference_Location

Rodos

Print_ISBN

0-7803-3650-X

Type

conf

DOI

10.1109/ICECS.1996.584628

Filename

584628