DocumentCode :
3464994
Title :
Post-layout parasitic verification methodology for mixed-signal designs using fast-SPICE simulators
Author :
Sangameswaran, Sundaram ; Yamauchi, Sho
Author_Institution :
HPA-HVAL EDA, Texas Instrum. Inc., Dallas, TX, USA
fYear :
2005
fDate :
10 Oct. 2005
Firstpage :
211
Lastpage :
214
Abstract :
Current sub-100 nanometer processes employ complex multilayer metallization structures with advanced dielectric materials. Closely-spaced thin, tall metal interconnects with low voltage and fast-clocking edges lead to circuit performances dominated by parasitic delays. Various issues such as noise and delay associated with cross-talk due to coupling capacitances; IR drop effects in the low power supply operating regimes; high current density causing electromigration in narrow interconnect structures; and DC path leakage currents are becoming very common effects in recent mixed-signal designs. Full-chip, post-layout simulation with extracted parasitic components is required in the design flow to accurately analyze each of these effects. Due to the presence of a large amount of parasitics, it is important to extract appropriate parasitics for the relevant process corners and perform the analysis. Fast-spice simulator-based flows are becoming prevalent due to their capacity and efficiency in handling large amounts of data. In this paper, we discuss various options available for designers using fast-spice simulators (e.g. UltraSim, NanoSim, and HSIM) for post-layout simulations, and how these options affect the end results. We have simulated the design with 2.5 million RC elements in 13 hours using a fast-spice simulator. A few examples of post-layout simulations carried out on designs will be discussed.
Keywords :
SPICE; circuit layout CAD; electromigration; integrated circuit interconnections; integrated circuit layout; integrated circuit reliability; mixed analogue-digital integrated circuits; DC path leakage current; IR drop effect; coupling capacitance; cross-talk; dielectric material; electromigration; fast-SPICE simulator; mixed-signal design; multilayer metallization structure; post-layout parasitic verification; thin tall metal interconnects; Circuit noise; Circuit simulation; Crosstalk; Delay; Design methodology; Dielectric materials; Integrated circuit interconnections; Low voltage; Metallization; Nonhomogeneous media;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Architecture, Circuits and Implementtation of SOCs, 2005. DCAS '05. Proceedings of the 2005 IEEE Dallas/CAS Workshop:
Print_ISBN :
0-7803-9515-8
Type :
conf
DOI :
10.1109/DCAS.2005.1611173
Filename :
1611173
Link To Document :
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