Demodulating binary phase shift keyed signals using programmable logic devices

Author

Kikkert, C.J. ; Blackburn, C.

Author_Institution

Dept. of Electr. & Comput. Eng., James Cook Univ., Townsville, Qld., Australia

Volume

2

fYear

1999

fDate

1999

Firstpage

689

Abstract

This paper describes the realisation of a differential BPSK demodulator using a high speed ADC, an EPLD and an EPROM. By incorporating both I and Q data in the demodulation process, a significant improvement in performance is obtained. Computer simulation shows the bit error rate (BER) performance versus received carrier to noise ratio (CNR) is virtually identical to the theoretical performance of a differential phase shift keyed (DPSK) detector. The realisation of the special PLL required, to recover the data clock using an EPLD, a DAC, a conventional loop filter and VCO is described

Keywords

demodulators; digital phase locked loops; error statistics; phase shift keying; programmable logic devices; radio receivers; satellite communication; synchronisation; BER; DAC; EPLD; EPROM; I data; PLL required; Q data; VCO; binary phase shift keyed signals; bit error rate; conventional loop filter; data clock; demodulation; differential BPSK demodulator; high speed ADC; performance; programmable logic devices; received carrier to noise ratio; Binary phase shift keying; Bit error rate; Computer simulation; Demodulation; Detectors; Differential quadrature phase shift keying; EPROM; Phase detection; Phase noise; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing and Its Applications, 1999. ISSPA '99. Proceedings of the Fifth International Symposium on

Conference_Location

Brisbane, Qld.

Print_ISBN

1-86435-451-8

Type

conf

DOI

10.1109/ISSPA.1999.815765

Filename

815765